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This column appeared in the July issue of The PCB Magazine.
Today’s high-speed processors, SERDES interfaces and decreased time-to-market requirements are pushing design teams toward more nimble development processes. But there is no point in completing a design on time if it does not work! My motto is: “Simulate twice – build once.”
Figure 1 illustrates a Band-Aid solution which may be applied to fix a signal integrity (SI), crosstalk or radiation issue. This is obviously an afterthought and is not the most elegant solution to a problem. Unfortunately, simulation is engaged too often at the end of the design cycle to try to fix a problem, rather than before and during the process – fixing the problem at the source – to ensure design integrity.
Figure 1. Pre-layout simulation can eliminate more-costly Band-aid solutions on the back end of the design process.
Complex multilayer boards should be designed using a proven design methodology, incorporating pre-layout simulation before placing a single chip on the board. Simulation tools can be used to analyze various SI issues like reflections due to impedance mismatches, crosstalk, signal attenuation and power distribution network (PDN) noise – all of which can impact interconnect performance.
Simulation of a PCB design after placement and routing is recommended, but simulation early in the design process is even better. Both are, in fact, essential. Pre-layout analysis allows critical interface topologies, termination schemes, and I/O buffer selection to be defined and analyzed for synchronous, source-synchronous and clock recovery interfaces before placement and routing. This opens your eyes to what the circuitry is actually doing. It also leads to an enhanced perception of what might be a potential issue once the system is built.
Pre-layout simulation also allows a designer to identify and eliminate signal integrity, crosstalk and EMC issues early in the design process. This is the most cost-effective way to design a board with fewer iterations, rather than starting with the find-and-fix-based post-layout simulation.
There are multiple facets to pre-layout analysis, including:
- Stackup planning for controlled impedance, SI, crosstalk, and cost control
- Dielectric material selection for manufacturing yield, and high-frequency operation
- PDN optimization
- I/O buffer and drive strength selection
- Topology optimization
- Termination strategy
- Floor planning for critical components
- Deriving layout routing constraints, including trace width, spacing and length matching
- Signal Integrity analysis to meet the design specifications, with respect to noise margins, timing, skew, crosstalk, and signal distortion
Since I have already addressed the first three sections in previous articles, I will move on from there. I recommend using the ICD Stackup Planner and PDN Planner to simulate the design before diving into the steps described in the following paragraphs.
I/O Buffer and Drive-strength Selection
I/O buffer and drive-strength selection can be analyzed in pre-layout simulation. A vendor-provided IBIS model should contain all available drivers for each model, and may, for example, include buffer models with 8 mA, 12 mA, and 16 mA drive current. The mid-level 12 mA signal is generally required, unless there is a long transmission line with multiple loads. This may be the case on a mother board when driving a number of DIMM modules, for instance.
The schematic description that includes the arrangement of a network, its nodes, sequence, and connecting transmission lines is generically referred to as the interconnect topology. In order to avoid signal quality and timing problems, and to minimize manufacturing costs, thorough topology analysis is critical to the successful implementation of a high-speed interconnect. Ideally, this analysis should be done up-front before placement and routing.
Topology optimization involves:
- Selecting optimal topology style for signal integrity, timing and EMC
- Shortening traces and stubs to their critical length or shorter, where possible
The most basic topology is a simple point-to-point connection between a driver and receiver. This topology is commonly used for busses or otherwise grouped traces. A good example of this would be the data banks of DDR memory. Left unterminated, these traces may be too long (more than 1/10 rise time), and reflections become a problem.
Figure 2. DDR2 data signal with series terminator.
Figure 2 illustrates a Xilinx Virtex 4 transceiver driving a DDR2 data signal into a 53-ohm transmission line. The interconnect is three inches long – a little bit longer than normal. Initially, the signal was simulated with no series termination, resulting in the red waveform in Figure 3.
Reflections deteriorate signal quality and timing, and contribute to crosstalk and radiation. Figure 3 shows 790 mV of ring back (red waveform) caused by reflections. It should be noted that reflections are only of concern for interconnect lengths that exceed 1/10 of the driver’s rise time (in nanoseconds). Since a signal in a typical dielectric travels at about 6 inches per nanosecond (5.8 inches per nanosecond, if you want to be exact), you can divide the end-to-end interconnect length in inches by six to get the interconnect length in nanoseconds. If the driver’s edge rate is more than 1/10 this number, termination will be required, more often than not.
Figure 3. Ringing of the data signal due to reflections.
There are four primary types of termination types for single-ended signals, including DC parallel (a.k.a., a pull-up resistor), AC parallel, Thevinin, and series termination. In this article, we will focus on DC parallel and series termination, which are commonly employed in high-speed design. The value of the series terminator is calculated using the following relationship:
Rseries = Line impedance – source resistance
The ICD Stackup Planner can be used to calculate the transmission line impedance. The source resistance should be available in the driver datasheet, or can be obtained from the IBIS model.
Adding a 33-ohm series terminator close to the driver dampens the ringing to 200 mV, as shown by the green waveform in Figure 3.
Figure 4 shows the results of pre-layout simulation of a typical DDR2 data signal. In this case, the data signal did not need termination, saving a component, and a bit of board space, which is a savings that can add up on a high-volume product.
Figure 4. Pre-layout simulation of the data signal (MDQ0).
Another topology type is the multi-drop or daisy chain – commonly used when signals are distributed to multiple components. DDR2 address and clock lines are sometimes routed in this way. Far-end, DC parallel termination is often useful in multi-drop connections. In the DDR2 address case of Figure 5, this would be a VTT pull-up resistor at the end of each address line.
Figure 5. DDR2 address signal model.