Designer's Notebook: PCB Design for Bare Board Testing

There are several testing methods used for certifying that the circuit board meets its defined quality level and intended functional criteria. Multilayer circuit boards have become increasingly complex: finer conductor line definition, blind and buried microvia interface, and smaller, finer-pitch SMT land pattern geometries. Visual assessment using automated optical inspection (AOI) is adopted to check all circuit layers prior to lamination and as a final examination of the end product.

Flying probe testing, in particular, is a method that uses multiple contactors designed to make rapid electrical contact on exposed conductive terminal sites of the PCB surface. Users have found that the flying probe electrical test is very accurate; it is capable of quickly measuring the electrical characteristics of each board with a high accuracy, ensuring that the board meets the specifications of the design. Probe contactors rapidly move across the circuit board’s surface, allowing the test to be completed in a short amount of time. This is beneficial when time is of the essence, such as when a product needs to be released to market quickly. The probes travel across the surface of the board, making contact at pre-designated locations to verify interconnect integrity.

Compared to fixed-probe testing, the flying probe test is not dedicated to a single board design and can test a variety of circuit board designs using the same testing system. By utilizing the CAD data, the probes can be preset to comply with an unlimited number of circuit patterns, enabling the uncompromised testing of individual or panel format circuit boards. Finally, the flying probe test is safe. To prevent the probe contactors from coming into contact with any other components or people, the probes are protected by a guard, minimizing the risk of damage or injury caused by faulty circuit boards.

Flying probe testing is one of the most efficient and cost-effective methods of testing PCBs. It is accurate, fast, flexible, and safe, making it the ideal solution for many types of testing requirements. A leading circuit board fabricator in the Silicon Valley recommends:

  • Designated probe contact surfaces must be free of dielectric coatings, resist material, or solder mask
  • The preferred surface area provided for probe contact is 0.50 mm (~0.020")
  • Minimum probe contact area should not be less than 0.15 mm (~0.006")
  • When probing via holes, the preferred land diameter is 0.25 mm (~0.010") but, depending on the test system employed, they may range between 0.20 mm and 0.50 mm (~0.008" and 0.020") diameter

Vern_March23_Fig1_cap.jpgThe system shown in Figure 1 is equipped with eight probe heads (4X on the topside and 4X on the bottom) and can simultaneously probe both surfaces of the bare circuit board or panel, enabling micro-pad probe targets as small as 0.30 μm.

The test system can provide probing speeds up to 180 touches per second and accuracy in the range of ±10 μm, and repeatability of ±5 μm.

Circuit board manufacturers note that the manufacturing process of printed circuit boards is complex, and the process is cumbersome. Any defects not detected during the post etching phase of the manufacturing process, if not corrected, will seriously affect the quality of the final product. In order to effectively control the progression of quality defects in the production process, and prevent the imperfections from occurring on future runs, prompt corrective action is warranted.

The following identifies defects that may occur during the circuit board fabrication process:

  • Electroplating short circuit: When the copper conductors are closely spaced and equal in both height and width, copper bridging between circuit paths can occur. The cause of bridging is likely due to dry film resist breakdown during the plating process.
  • Copper bridge short circuit: A very thin wire-like copper connection between two conductors forming a short circuit. The cause may be attributed to foreign particles that remain trapped between the resist film and copper surface.
  • Insufficient etching: Where random copper blotches remain in the open, copper-free area, and where closely spaced conductors run in parallel for long distances. This may be due to etch chemical imbalance or when the duration for the etching process is too short.
  • Scratch short circuit: When a short circuit remains after electroplating and etching. Typically attributed to scratches in the dry film resist by mechanical, human contact, or hair and other fine fibers falling on the board surface. These particles, if not removed before imaging and electroplating, will impede light access, resulting in copper bridging.

Overall, the flying probe test is an efficient and cost-effective method for testing circuit boards after fabrication is completed. It is accurate, fast, flexible, and safe, making it the ideal solution for many types of testing requirements. However, when the circuit board fails during electrical testing, there are other testing methods that can be implemented to identify defects.

The 3D X-ray inspection systems can provide 3D images of the circuit board by creating a series of 2D cross-sections to expose defects embedded in the board after lamination. While removing the defect on the inner layers of the board may not be practical, identifying and discarding a specific circuit board within a multiple unit panel format will ensure that it does not reach assembly. The images shown in Figure 2 represent the isolated X-ray view of defects within the inner-layer circuit conductor routing path.

Vern_March23_Fig2_cap.jpg

In addition to visual and X-ray imaging, thermal imaging, EMI test, and solderability testing is often implemented to further certify that all boards are manufactured correctly and will be assembly process ready, and that any design flaws that would compromise product reliability are identified and corrected.

This column originally appeared in the March 2023 issue of Design007 Magazine.

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2023

Designer's Notebook: PCB Design for Bare Board Testing

03-22-2023

There are several testing methods used for certifying that the circuit board meets its defined quality level and intended functional criteria. Multilayer circuit boards have become increasingly complex: finer conductor line definition, blind and buried microvia interface, and smaller, finer-pitch SMT land pattern geometries. Visual assessment using automated optical inspection (AOI) is adopted to check all circuit layers prior to lamination and as a final examination of the end product.

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Designers Notebook: Flexible Circuits for In-line SMT Assembly Processing

01-20-2023

Incorporating surface mount components directly onto a flexible circuit’s etched copper land patterns is not unlike the assembly process used for rigid circuit boards. To maximize robotic assembly efficiency and increase throughput of the flexible circuit, however, the circuit design engineer will need to provide a format that includes all features required for in-line assembly processing.

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2022

Designers Notebook: Ultra High-Density Circuit Board Design

11-03-2022

To facilitate new generations of high I/O semiconductor packaging, circuit board technology is undergoing significant refinement in both fabrication process methods and base materials selected. Many of the new high-function semiconductor package families require significantly more terminals than their predecessors. Interconnecting these very fine-pitch, high I/O semiconductors can dramatically affect the procedures used in both circuit board design and assembly processing.

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Designers Notebook: Design for Test, Part 3

05-04-2022

The general trend in electronics is to improve performance and minimize product size, often leading to more complex printed circuit board and higher component density. Semiconductor packaging in particular, have become more complex, many having multiple functions interconnected within the package or onto the silicon itself. For products with very high component density companies soon realize that 100% test-probe access may not be possible.

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Designers Notebook: Design for Test, Part 2

03-08-2022

Current generations for PCB designs have increased in complexity. The product developer and assembly service provider, whether in-house or outsourced, must consider manufacturing efficiency, throughput, and process yield. While design for manufacturing is an absolute necessity for controlling manufacturing costs, design to accommodate product testing does need attention as well. The primary concern is to ensure that the end product will perform reliably without compromise.

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Designers Notebook: A Lesson on Automated Optical Shaping

03-07-2022

IPC APEX EXPO show and conference was safely back in full swing after skipping 2021. Because my primary interest is printed circuit board and assembly processing, I ventured onto the show floor to review some of systems exhibited that have evolved that may contribute to process efficiency and end product quality. A key benefit of attending a show like this one is that the board and assembly manufactures can view and compare similar product offerings in one place.

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Designer's Notebook: Design for Test, Part 1

02-03-2022

Circuit board fabricators remind us that multilayer boards will predictably have more components necessitating greater circuit routing complexities than that experienced on earlier applications. Also, with each generation of semiconductors it seems that the terminal count increases and the spacing between terminals shrinks, requiring designers to employ conductor lines and spaces that are far narrower than previously considered the norm.

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2021

Designers Notebook: Embedding Resistor Elements—Part 2

06-15-2021

As an alternative to the thick-film resistor process detailed in Part 1, a significant number of PCB fabricators are offering embedded thin-film resistor capability. Read Part 2 here.

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Designers Notebook: The 'New and Growing' Embedded Resistors

04-19-2021

Why is embedded resistor technology considered to be “new” and “growing” despite decades of history? In fact, a broad number of established PCB fabricators are knowledgeable about the materials and processes for embedding resistor elements but not all may be prepared to alter procedures established for their more conventional multilayer circuit board customer base.

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Designers Notebook: Developing Panel Level Semiconductor Packaging

02-22-2021

While semiconductor packaging has traditionally utilized a narrow strip of organic copper-clad organic-based laminate and wire-bond processing for the single-die BGA. Companies furnishing devices for high-volume markets are now implementing very fine-pitch alloy bumped flip-chip package technologies that enable face-down interface.

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2020

Designers Notebook: Panel-level Semiconductor Package Design Challenges

05-15-2020

Semiconductor package specialists continually work to improve high-volume manufacturing process efficiencies while reducing manufacturing costs. A majority of the commercial semiconductors are built-up on the surface of a circular-shaped silicon wafer with metalized terminal features at their perimeter to accommodate wire-bond interface with a lead-frame or package substrate. Vern Solberg explains.

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Designers Notebook: Design Challenges for Developing High-density 2.5D Interposers, Part 2

01-29-2020

In Part 2 of his column series on design challenges for high-density 2.5D interposers, Vern Solberg discusses primary base materials for 2.5D interposer applications, design guidelines, technical challenges, and key planning issues.

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Designers Notebook: PCB Design and HD Semiconductor Packaging

01-15-2020

To better meet their performance and miniaturization goals, manufacturers are looking for higher functionality for their semiconductor packages. For that reason, many manufacturers will rely heavily on more innovative IC package solutions, often integrating a number of already proven functional elements within a single-package outline. Vern Solberg covers how this and more impact PCB design and HD semiconductor packaging.

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2019

Designers Notebook: Focus of Interest at SMTAI 2019—Low-temperature Solder

10-03-2019

Both suppliers and users of solder materials participated in discussions at SMTAI 2019 related to low-temperature solder (LTS). The solder supply companies present had a wide range of material compositions that employed elements of bismuth or indium to reduce the liquidus temperature of the alloy during the joining process. Key issues that user companies are concerned with are the lower-temperature alloys selected must be reliable and exhibit shear strength, creep resistance, and resistance to thermal fatigue for the duration of the product’s life cycle.

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Designers Notebook: Embedding Components, Part 7—Semiconductor Placement and Termination Methodologies

03-11-2019

Progress in developing high-density embedded-component substrate capability has accelerated through the cooperation and joint development programs between many government and industry organizations and technical universities. In addition to these joint development programs, several independent laboratories and package assembly service providers have developed a number of proprietary processes for embedding the uncased semiconductor elements.

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Embedding Components, Part 6: Preparation for Active Semiconductor Elements

01-10-2019

Designers are well aware that a shorter circuit path between the individual die elements, the greater the signal transmission speed, which significantly reduces inductance. By embedding the semiconductors on an inner layer directly in line with related semiconductor packages mounted on the outer surface, the conductor interface distance between die elements will be minimized.

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