The Plating Forum: DIG—The Next Generation

DIG stands for “Direct Immersion Gold.” The acronym is used to specify direct deposition of gold on copper as a surface finish. It is a metallic solderable finish. At assembly, DIG forms a Cu/Sn intermetallic with the gold layer dissipating into the bulk solder. DIG has been around for at least 15 years.

Gold will readily immerse on copper based on their respective positions in the EMF series. The reaction is driven by +1.22 volts. As in all immersion reactions, the reaction will continue as long as the substrate is available to the displacement reaction. As the substrate is covered by the depositing species, it becomes less available, rendering the reaction self-limiting.

The original formulation of DIG produced a relatively thin gold layer that had a reddish hue to it from the partial diffusion of copper. Copper diffusion to the surface continued with time; after a year of storage at ambient conditions the deposit color became increasingly reddish, almost brown. Checking the solderability of the discolored surface using wetting balance methods showed excellent wetting and no signs of soldering degradation.

At that time, DIG did not seem to offer any breakthroughs as other established finishes like OSP, immersion silver, and immersion tin. These surface finishes were well-established, their limitations were well understood, and they were deployed extensively in PCB manufacturing. DIG was a more costly finish and created apprehension as it was clear that the copper would diffuse through the immersion grain boundaries into the gold, altering the as-received surface.

A new generation of DIG was developed to meet the needs for wire bonding and high frequency signal propagation. High frequency RF signal loss is associated with thicker nickel deposits. The new DIG process uses a reduction-assisted immersion gold (RAIG). The use of an RAIG gold allowed for the deposition of a thicker gold layer up to 0.3 µm (12 µins) that prevented the diffusion of copper to the surface. 

During deposition the immersion gold initiates on the copper surface and that triggers the electroless deposition, which will continue to deposit as the copper substrate gets plated over and is no longer available to sustain the immersion reaction. The electroless reaction does not require substrate contribution as it is driven by a reducing agent in the electrolyte. The electroless deposit is non-granular and not porous. Unlike the original immersion DIG, this new mode of deposition can produce a thicker layer that is pore-free (no grain boundaries) thus limiting the migration of copper. The deposit has the lemon-yellow color that is expected of a gold deposit in contrast with the reddish yellow of the original DIG. At 0.2 to 0.3 µm, the deposit shows no signs of copper diffusion to the surface.

Hofstetter PCB AG in Küssnacht/Switzerland is a supplier of various coatings in microelectronics. Hofstetter supplies a complete spectrum of surface finish plating to the microelectronics industry. They offer some of the newer finishes like EPIG (electroless palladium immersion gold), ISIG (immersion silver immersion gold), and DIG (direct immersion gold). Their R&D department invests in studying the properties of some of the newer finishes coming to the market, exploring solutions to meet the ever-changing demands of their customers.

Hofstetter has conducted a comprehensive study on the gold wire bondability of the new DIG process.

They studied the consistency and strength of the gold wire bonds under different temperatures, namely 90–130oC for the wedge bond and 150oC for the first (ball) bond. They included room temperature bonding in the study. Room temperature bonding has a narrow operating window compared to a heated table. Success at room temperature bonding was achieved by the optimization of the DIG surface topography and the US (ultrasound) bonding force. The study concluded that the new DIG at 8-12 µins (0.2–0.3 µm) thickness is capable of producing wire bonds consistently and reproducibly with optimized bonding parameters.

The DIG surface at 8–12 µins exhibits a distinct fine roughness, which is very evenly formed over the entire surface. The new DIG surface requires minimum processing steps. Deposition requires a standard cleaner and micro-etch followed by the gold bath. This contrasts with ENEPIG which requires cleaner, micro-etch, catalyst, electroless nickel, electroless palladium, and immersion gold.

The new DIG is a surface finish that offers advantages over the traditional finishes like OSP, immersion silver, and immersion tin. OSP is a fragile, organic solderability preservative that cannot be used as a contacting surface. Immersion silver is a good contacting surface but was susceptible to creep corrosion and occasionally formed voids at the IMC surface. Immersion tin will form a Cu/Sn intermetallic during storage and may lose some of its wetting properties at assembly.

The new DIG, which is commercially available today, is solderable and aluminum and gold wire bondable, and it is ideally suited for plating small features with limited spacing. The absence of nickel in the surface finish makes it well-suited for high frequency applications.

This column originally appeared in the June 2021 issue of PCB007 Magazine.                                                                                                                                                         

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2021

The Plating Forum: DIG—The Next Generation

06-16-2021

DIG stands for “Direct Immersion Gold.” The acronym is used to specify direct deposition of gold on copper as a surface finish. It is a metallic solderable finish. At assembly, DIG forms a Cu/Sn intermetallic with the gold layer dissipating into the bulk solder.

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The Plating Forum: RAIG (Reduction Assisted Immersion Gold) for Gold Surface Finishes

04-05-2021

RAIG was introduced a few years ago to meet the requirements of newer designs. Since its inception, more gold finishes are finding RAIG gold to be a viable alternative to standard immersion gold. RAIG gold is a mixed reaction bath that functions as an immersion gold and with the added reducing agent it also functions as an electroless (autocatalytic) bath.

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2020

The Plating Forum: Training for Plating Processes in the Electronics Industry

12-24-2020

Plating is a very old industry and has been studied for many generations. Its basic principles are well understood and documented. However, when it comes to the intricate details of plating a circuit board, there is so much to learn and apply. George Milad explains.

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The Plating Forum: Via Plating for PWBs

11-19-2020

Vias are an integral part of PWB design and manufacturing. They are the means by which different layers of a board are connected. George Milad addresses the electroplating of vias, including the three main types of vias: through-hole vias, buried vias, and blind vias.

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The Plating Forum: The Critical Role of Pretreatment for Plating

10-22-2020

Pretreatment is usually customized to the incoming substrate and the plated metal. George Milad explains how it is a critical step and must be completed before plating to achieve the desired adhesion and to enhance the quality of the deposited metal.

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The Plating Forum: Immersion Plating Reaction in Electronics Manufacturing

09-16-2020

Plating or metal deposition is a key component in the manufacturing of electronic packages (circuit boards and integrated circuits). Plating occurs when a metal ion in solution (electrolyte) is reduced to the metal. The reduction takes place when electrons are supplied to the ion. George Milad dedicates this column to the immersion reaction.

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The Plating Forum: Minimizing Signal Transmission Loss in High-Frequency Circuits

07-06-2020

All PCB materials have both conduction and dielectric RF signal losses. In this column, George Milad highlights resistive conduction losses by the copper layer used in the board.

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The Plating Forum: Can ‘Nickel Corrosion’ Occur in ENEPIG?

05-25-2020

Nickel palladium gold (ENEPIG) surface finish is being referred to as the “universal finish.” ENEPIG was also the answer to the nickel corrosion “black pad” encountered occasionally with electroless nickel/immersion gold (ENIG) deposits. In this column, George Milad answers the question, "Can 'nickel corrosion' occur in ENEPIG?"

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The Plating Forum: Eliminating Waste From Electrolytic Acid Copper Plating

03-15-2020

Acid copper plating in most shops is done in vertical plating tanks. Acid copper solutions are not dumped but are continuously used with occasional carbon treatment to remove organic build-up from the additives and from dry film leaching. George Milad explains.

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The Plating Forum: EPIG—A Nickel-free Surface Finish for Next-generation Products

01-11-2020

In recent years, electronic devices, such as smartphones and tablet PCs, have been miniaturized. Chip-size package (CSP) used inside the electronic devices have been miniaturized as well, and the spacing between the lines continues to diminish every year. Some of the latest packages have spacing as little as 15 µm or less. If electroless nickel electroless palladium immersion gold (ENEPIG) is used with an EN thickness of 5–6 µm, only 5 µm of spacing would be left, increasing the risk of shorts between the traces. George Milad explains.

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2019

The Plating Forum: New Developments in ENIG

12-08-2019

ENIG has been around the printed circuit industry for more than 25 years. George Milad provides an update and explains how although the occurrence of corrosion was recognized, a better understanding of the defect has led to a series of improvements over time.

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The Plating Forum: Update on IPC-4552 ENIG Specification Revisions

10-20-2019

George Milad's columns will cover PCB plating, IPC specifications, and more. In this debut installment, he gives us an update on the IPC-4552 ENIG specification, including Revision A and B.

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2014

The Plating Forum: Wire Bonding to ENIG

03-05-2014

The IPC-4552 ENIG specification was written in 2002, but the committee is currently updating and revising the document. The thickness of the immersion gold layer is being revised with the intent of reducing the minimum thickness from 2.0 µin to 1.6 µin. A series of studies were conducted to find out if this reduction is possible.

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The Plating Forum: ENIG and the Plating Process

01-07-2014

ENIG continues to gain market share due to its versatility in a wide range of component assembly methods including solder fusing, wave soldering, and wire bonding. The plating of ENIG is a complex multi-step process. Each process step is carefully designed and must be well understood and controlled to produce the desired end product. George Milad reports.

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2013

Acid Copper Plating for High Aspect Ratio and Via Fill

07-16-2013

To meet new specification requirements, board shops are forced to seek new and advanced processes in every department. Acid copper plating comes under heavy scrutiny, as it is the process that forms the traces and the through-hole connectivity that conveys the signal from end-to-end of the final device. George Milad, a new columnist for The PCB Magazine, explains.

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